Target devices such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and structured ASICs are used to implement large systems that may include millions of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are high-level compilation and hardware description language (HDL) compilation. High-level compilation (or “high-level synthesis”) involves generating an HDL of a system from a computer language description of the system. HDL compilation involves performing synthesis, placement, routing, and timing analysis of the system on the target device.
When developing circuits on a spatial architecture, the circuits can be implemented as spatially distinct. This is necessary when the circuits perform different functions. When the circuits implement the same function, it may not be necessary to spatially replicate the implementation. In the realm of virtualization, where multiple clients may wish to access the same hardware resource, another option is to implement a single circuit and share it among the clients. In both scenarios, trust and isolation between individual clients are important considerations.